1. Field of the Invention
The present invention relates generally to automatic placement and routing techniques used in designing system large scale integrated circuits (LSIs) and particularly to automatic placement and routing apparatuses capable of automatic placement and routing of LSIs to for example allow LSI chips to have small areas and wiring resources to be less consumed, and reduce an effect attributed to voltage drop.
2. Description of the Background Art
In recent years, as LSI has been increasingly highly integrated, voltage drop has increasingly contributed to disadvantageously impaired performance of semiconductor device. This impaired performance can be improved by inserting a capacitive cell under a main power supply line to increase the line's wiring capacitance.
This capacitive cell, however, is inserted under the main power supply line manually after a layout design has been completed. This results in an LSI chip from having a disadvantageously increased area.
Furthermore, it depends on the designer's experiences and guesswork how many capacitive cells should be inserted. As such it has been difficult to determine an optimal number of capacitive cells to be inserted and their optimal positions for insertion.